Search for Author, Title, Keyword
Stress evolution mechanism and thermo-mechanical reliability analysis of copper-filled TSV interposer
Yuan Chen 1,2
Wei Su 2
More details
Hide details
Center for System Reliability and Safety, School of Mechanical and Electrical Engineering University of Electronic Science and Technology of China, Sichuan, 611731, P. R. China
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The Fifth Electronics Research Institute of Ministry of Industry and Information Technology, Guangdong, 510610, P. R. China
Publication date: 2020-12-31
Eksploatacja i Niezawodność – Maintenance and Reliability 2020;22(4):705–714
  • The stress evolution mechanism of TSV under thermal cycling was confirmed first time.
  • The relationship between the stresses state and failures of TSV interposer was found.
  • An original combined use of FEM simulation and failure analysis was proposed for TSV.
Through silicon via (TSV) has become one of the key emerging trends of three-dimensional (3D) packages, as it can realize vertically interconnect between stacked-dies. Due to large mismatch in thermal expansion coefficients (CTE) between the copper via and the silicon, significant mechanical stresses are induced at the interfaces when TSV structure is subjected to thermal stresses, which would greatly affect the reliability and electrical performance of TSV 3D device. In this paper, the relationship between the state of stresses and failure of TSV had been explored by combining finite element model simulation (FEM) and failure physical analysis. The position of the maximum stress of the TSV structure was obtained by FEM analysis. The relationship of stress and displacement change with temperature was also studied. And a thermal cycling experiment was conducted to validate the simulation results. Physical failure analysis after thermal cycling experiment was used to verify the degradation mechanism predicted by thermo-mechanical simulation.
Altmann F, Petzold M. Innovative failure analysis techniques for 3-D packaging developments. IEEE Design and Test 2016; 33 (3): 46-55,
Altmann F. Failure analysis strategies for multi-stacke d memory devices with TSV interconnects. Geophysical Journal International 2015; 189(3):1237–1252,
Annuar S, Mahmoodian R, Hamdi M, Tu K N. Intermetallic compounds in 3D integrated circuits technology: a brief review. Science and Technology of Advanced Materials 2017;18(1): 693-703,
Balac M , Grbovic A , Petrovic A , Popovic V. FEM analysis of pressure vessel with an investigation of crack growth on cylindrical surface. Eksploatacja i Niezawodnosc - Maintenance and Reliability, 2018; 20(3):378-386, 10.17531/ein.2018.3.5.
Beyne E. The 3-D Interconnect Technology Landscape. IEEE Design and Test 2016; 33 (3): 8-20,
Brand S, Altmann F. Lock-In-Thermography, Photoemission, and Time-Resolved GHz Acoustic Microscopy Techniques for Nondestructive Defect Localization in TSV. IEEE Transactions on Components, Packaging and Manufacturing Technology 2018; 8 (5):735-744,
Budiman A S, Shin H A S, Kim B J, Hwang S H, Son H Y, Suh M S, Chung Q H, Byun K Y, Tamura N, Kunz M. Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits. Microelectronics Reliability 2012; 52(3):530-533,
Chan J M, Tan C S, Lee K C, Cheng X, Kanert W. Reliability Evaluation of Copper (Cu) Through-Silicon Vias (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA). Proceedings of 67th Electronic Components and Technology Conference 2017; 1: 73-79,
Chudzik A, Warda B. Fatigue Life Prediction of A Radial Cylindrical Roller Bearing Subjected to A Combined Load Using FEM. Eksploatacja i Niezawodnosc - Maintenance and Reliability 2020; 22(2):212-220,
Chukwudi O, June W L, Fardad G, Klaus H, Obeng Y S. A Detailed Failure Analysis Examination of the Effect of Thermal Cycling on Cu TSV Reliability. IEEE Transactions on Electron Devices 2014; 61 (1): 15-22,
Coudrain P, Souare P, Dumas S, Chancel C, Farcy A. Experimental Insights into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Design and Test 2016; 33 (3): 21-36,
Croes K, Messemaeker J D, Li Y, Guo W, Pedreira O. Reliability Challenges Related to TSV Integration and 3-D Stacking. IEEE Design and Test 2016; 33 (3): 37-45,
Feng W, Watanabe N, Shimamoto H, Aoyagi M, Kikuchi K. Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation. Microelectronics Reliability 2019; 99(99): 125-131,
Frank T, Moreau S, Chappaz C, Leduc P, Arnaud L, Thuaire A, Chery E, Lorut F,Anghel L, Poupon G. Reliability of TSV Interconnects:Electromigration, Thermal Cycling, and Impact on above Metal Level Dielectric. Microelectronics Reliability 2013; 53 (1):17-29,
Gambino J P,Adderly S A, Knickerbocker J U. An overview of through-silicon-via technology and manufacturing challenges. Microelectronic Engineering 2015; 135: 73-106,
Gaudestad M J, Orozco A, Wolf I D, Wang T,Webers T. Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains.Proceedings of 40th International Symposium for Testing and Failure Analysis 2014; 2014: 38-42,
Huang L, Deng Q, Li M, Feng X, Gao L. A View on Annealing Behavior of Cu-Filled Through-Silicon Vias (TSV). ECS Journal of Solid State Science and Technology 2016; 5 (7): 389-392,
Jeong I H, Roh M H, Jung F, Song W H, Mayer M,Jung J P. Analysis of the Electrical Characteristics and Structure of Cu-Filled TSV with Thermal Shock Test. Electronic Materials Letters 2014; 10 (3): 649-653,
Jiang T, Im J, Huang R, Ho P S. Through-silicon via stress characteristics and reliability impact on 3D integrated circuits. Mrs Bulletin 2015; 40 (3): 248-256,
Kumar P,Dutta I,Bakir M S. Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV). Journal of Electronic Materials 2012; 41 (2): 322-335,
Lau J H. Overview and outlook of three-dimensional integrated circuit packaging, three-dimensional Si integration, and three-dimensional integrated circuit integration. Journal of Electronic Packaging 2014; 136 (4): 040801,
Lee C C, Lin Y M, Hsieh C P, Liou Y Y, Zhan C J,Chang T C,Wang C P. Assembly Technology Development and Failure Analysis for Three-Dimensional Integrated Circuit Integration with Ultra-Thin Chip Stacking. Microelectronic Engineering 2016; 156:24-29,
Li G, Chen Z, Cao S, Luo H, Jiang L, Zhu W. Failure Analysis on the Mechanical Property of Through-Silicon Vias Interface Using A Cohesive Zone Model. Proceedings of 17th International Conference on Electronic Packaging Technology 2016; 1341-1345,
Liu D , Wang S , Tomovic M . Degradation modeling method for rotary lip seal based on failure mechanism analysis and stochastic process. Eksploatacja i Niezawodnosc - Maintenance and Reliability 2020; 22(3):381-390,
Liu Y, Wang Y S, Fan Z W, Hou Z Q, Zhang S F, Chen X. Lifetime prediction method for MEMS gyroscope based on accelerated degradation test and acceleration factor model. Eksploatacja i Niezawodnosc - Maintenance and Reliability 2020; 22(2):221-231,
Pan Y, Li F, He H, Li J, Zhu W. Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging. Microelectronics Reliability 2017; 70: 97-102,
Rodríguez, J M, Carbonell Puigbó, Josep Maria, Cante Terán, Juan Carlos. The particle finite element method (PFEM) in thermo-mechanical problems. International journal for numerical methods in engineering 2016; 107(9): 733-785.
Shen W W, Chen K N. Three-dimensional integratedcircuit (3D IC) key technology: through-silicon via (TSV). Nanoscale Research Letters 2017; 12: 56,
Villar A V Q D , Luis Rodríguez-Picón, Olguin I P , Gonzalez L M. Stochastic modelling of the temperature increase in metal stampings with multiple stress variables and random effects for reliability assessment. Eksploatacja i Niezawodnosc - Maintenance and Reliability 2019; 21(4):654-661,
Wang F, Yu N. An Effective Approach of Improving Electricaland Thermo-Mechanical Reliabilities of Through-Silicon Vias. IEEE Transactions on Device and Materials Reliability 2017; 17:106-112,
Wang Z B, Li W Y, Shang S, Wang Z, Han C Y. Performance degradation comparisons and failure mechanism of silver metal oxide contact materials in relays application by simulation. Eksploatacja i Niezawodnosc - Maintenance and Reliability 2019; 22(1):86-93,
Yoon H, Choi K S, Bae H C, Moon J T, Eom Y S, Jeon I. Evaluating the material properties of underfill for a reliable 3D TSV integration package using numerical analysis. Microelectronics Reliability 2017; 71: 41-50,
Microstructure evolution and protrusion of through silicon via copper (TSV-Cu) considering different annealing heating rates
Min Zhang, Yanwei Dai, Fei Qin, Yifan Jin
2022 23rd International Conference on Electronic Packaging Technology (ICEPT)
Protrusion of Through-Silicon-Via (TSV) Copper with Double Annealing Processes
Min Zhang, Fei Qin, Si Chen, Yanwei Dai, Pei Chen, Tong An
Journal of Electronic Materials
Fatigue life prediction of wire rope based on grey particle filter method under small sample condition
Dan Zhao, Yu-Xin Liu, Xun-Tao Ren, Jing-Zi Gao, Shao-Gang Liu, Li-Qiang Dong, Ming-Shen Cheng
Eksploatacja i Niezawodnosc - Maintenance and Reliability
Internal defects inspection of TSV 3D package based on thermal distribution analysis
Lei Nie, Yifan Huang, Mengran Liu
AIP Advances
Correlations between Microstructure and Residual Stress of Nanoscale Depth Profiles for TSV-Cu/TiW/SiO2/Si Interfaces after Different Thermal Loading
Min Zhang, Fangzhou Chen, Fei Qin, Si Chen, Yanwei Dai
Holding time effect on mechanical properties and protrusion behaviors of through silicon via copper under various annealing processes
Min Zhang, Fei Qin, Si Chen, Yanwei Dai, Yifan Jin, Pei Chen, Tong An, Yanpeng Gong
Materials Science in Semiconductor Processing
Analysis of Thermomechanical Stresses in Silicon During Heating of Aluminum Interconnects on its Surface by a Pulse Current
Arkady Skvortsov, Vladimir Nikolaev, Marina Koryachko, Pavel Skvortsov, Evgeniy Volkov
Effect of Capped Cu Layer on Protrusion Behaviors of Through Silicon via Copper (TSV-Cu) Under Double Annealing Conditions: Comparative Study
Min Zhang, Fei Qin, Si Chen, Yanwei Dai, Yifan Jin, Pei Chen, Tong An, Yanpeng Gong
IEEE Transactions on Device and Materials Reliability